A dry-wet Quasi-ALE (Q-ALE) process is demonstrated for tungsten, combining self-limiting O2 plasma oxidation with timed wet-chemical oxide removal in 1 M HCl solution at room temperature (RT). Inductively coupled plasma mass spectroscopy (ICP-MS) and electrochemical measurements were used to study oxide dissolution kinetics. Quantification revealed an initially high etch rate of the surface that gradually decreased and stabilized to a low background value. This evolution is attributed to the rapid dissolution of the plasma-generated bulk WO3, followed by the slower removal of the interfacial suboxide layer. Subsequently, the process reached a steady-state regime characterized by trace residual oxide coverage and a background etch driven by simultaneous reoxidation and metal dissolution. Although the background contribution is low, the removal step is halted before its onset to ensure controlled and selective material removal. These results were complemented by post operando X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM) and conductive atomic force microscopy (C-AFM) measurements. An etch rate of 8 & Aring;/cycle was achieved and validated on both blanket and patterned films deposited by physical vapor deposition (PVD) and atomic layer deposition (ALD) using industrial-scale equipment. This demonstrates the lab-to-fab scalability of the process, thereby enabling angstrom-level precision for advanced semiconductor manufacturing.

The continuous expansion of two-dimensional materials research since the first developments of over 15 years ago has enabled tremendous progress in the fundamental understanding of their properties and behavior. The promises held by these materials to facilitate scaling beyond silicon-based device architectures are still valid, but the manufacturability and integration with silicon technology remain challenging. On the metrology side, characterization of the device channel and assessment of the expected performance is lacking, at least in a fully non-destructive and process line-compatible implementation. The current paper demonstrates a clear correlation between metrics associated with the transistor performance on one hand, and parameters from photoluminescence spectra on the other. The concept is demonstrated on state-of-the-art 300 mm process MoS2 devices, without the need for specific measurement conditions or sample preparation. Being truly non-contact and relatively fast, this analysis provides the community with a potential route toward non-invasive material quality assessment, applicable at several stages of the process and with a direct connection to device performance.

CFETs based on 2D materials hold the potential to replace Si as a channel at advanced technology nodes. In this work, gate-all-around (GAA) nanosheet FETs with the monolayer MoS2 channels are presented. The MoS2 monolayer was successfully suspended above the oxide trench of varying lengths. Less than 20% sag was observed up to a trench length of 200 nm. For the first time, a gate-first process, in combination with critical point drying, is introduced to scale down GAA nanosheet FETs to 50 nm channel width and length without introducing damage to the monolayer MoS2. Perfect conformal gate stack deposition on the monolayer MoS2 sheets is achieved by using TMA 'soaking' treatment. The successful demonstration of monolayer GAA 2D nanosheet FET further shows high potential as a basic component for the future 2D CFET chips integration.

In this work, stacked nanosheet FETs with monolayer MoS2 channels are presented. At a channel length of 40 nm, the transistor exhibits a remarkable $\mathrm{I}_{\text{ON}}-451\ \mu \mathrm{A}/\mu \mathrm{m}$ at $\mathrm{V}_{\text{DS}}=1\ \mathrm{V}$, achieved with two tiers of monolayer-MoS2 channels. The device has a record $\mathrm{I}_{\text{ON}}/\mathrm{I}_{\text{OFF}} > 10^{9}$ and a yield of 96.59%, which shows good electro-static control in the nanosheet channels. We compare these results to dual gate 2D FETs and show how learnings on the planar devices can be utilized in a gate-all-around case. The successful demonstration of stacked 2D nanosheet FETs with high performance further extends Moore's Law scaling with the future 2D CFETs application.

Surface polarity plays a significant role in chemical etching of GaN in KOH solution, a process that is important for quality control and device fabrication. In this work, basic chemical mechanisms are proposed to explain the role of surface orientation in the chemical etching of the semiconductor. In addition, it is shown how prior photoetching of inert surfaces [the polar (0001), semipolar (101 (1) over bar), and nonpolar (1 (1) over bar 00) interfaces] enables chemical etching. Photoetching gives rise to the formation of nanocolumns on dislocations and to protrusions on nanoscale inhomogeneities. Subsequent etching in KOH solution leads to the development of distinctive features that depend on the crystal orientation of the surface and the presence of the inhomogeneities. The morphology of the photoetched surfaces was revealed by scanning electron microscopy, while X-ray photoelectron spectroscopy measurements were used to investigate the surface chemistry of these processes.

Anisotropy in the wet-chemical surface oxidation of indium arsenide (InAs) (111) in HCl/H2O2 and H2SO4/H2O2 was investigated. The atomic-scale etching kinetics was determined by inductively coupled plasma mass spectrometry and the surface chemistry, and electronic property transformation was probed by post operando synchrotron X-ray photoelectron spectroscopy. The oxidation rate is found to be larger for the (111)-B surface (As-terminated) than for the (111)-A surface (In-terminated). HCl/H2O2 solution has shown lower InAs etch rates than H2SO4/H2O2. The nature of etchant plays a role in the band bending, which is attributed to the formation of different species (sulfates/sulfides, chlorides, and hydroxides) on the surface. (C) 2021 Elsevier Ltd. All rights reserved.

In this atomic-scale study on technologically relevant group IV semiconductors, Ge and SiGe, we relate surface chemistry, in particular the nature of surface oxides, to wet etching kinetics. ICP-MS quantification of Ge in HCl solution containing H2O­2 as the oxidizing agent showed that the Si bulk concentration strongly impacted the etching kinetics. Post operando synchrotron XPS provided insight into the surface oxide chemistry involved in the etching process: a non-homogeneous porous layer with a depletion of Ge components at the outer surface due to pull out effects.

Over the decades, Si-based complementary metal–oxide semiconductor (CMOS) technology has challenged the semiconductor industry in improving device performance while maintaining the scaling requirements. However, the use of the group IV semiconductor as a channel material is reaching its ultimate limit due to physical complications, such as gate leakage, parasitic resistance/capacitance and size channel effects [1]. Some workaround solutions have implemented trigate structures, while novel gate-all-around (GAA) nanowire or nanosheet devices are also explored.[2] One of the core challenges for these devices is the highly selective removal of sacrificial SiGe epitaxial layers to release active parts of the device.[3] This aspect is further complicated by the introduction of Ge as an alternative channel material of higher mobility.[4] Wet-chemical processing remains an essential step for new nanodevice fabrication. With channel widths of only a few tens of atomic layers, etching control up to the atomic-layer-scale is necessary. To achieve such a level of precision, basic insights in semiconductor/electrolyte interactions are indispensable. Unlike for Si, the surface chemistry of Ge in wet-chemical solutions has remained relatively unexplored. One of the factors impeding in-depth surface analysis is the high reactivity of Ge in air. For this reason, the use of an integrated surface preparation apparatus in a surface analytical tool is crucial to rule out controversial effects of atmospheric oxygen and water. In this work we discuss the wet-chemical etching of Ge (100) in acidic H2O2 solutions. Kinetic studies were performed using inductively coupled plasma mass spectrometry (ICP-MS). Under reaction limited conditions, we showed that surface chloride chemistry has a profound impact on the dissolution kinetics and the anisotropy of wet etching, while proton effects were found to be less important. These results served as a starting point for the comparison of Ge versus SiGe. We provide an atomic scale investigation on the influence of the Si bulk concentration versus the kinetics of etching. The results are complimented by synchrotron X-ray photoemission spectroscopy (SXPS) measurements. We highlight the use of an integrated surface preparation chamber directly connected to SXPS apparatus to obtain fundamental insights into the surface chemistry of these technologically relevant group IV semiconductors. The results suggest that, while the release of Ge atoms from surface sites is favorable, the Si oxide chemistry determines the etching kinetics of SiGe. Basic etching schemes help to explain the formation of a (quasi) self-limiting oxide on SiGe. Energy dependent surface composition analysis provided insight into the nature of the oxide layer that showed depletion of Ge components at the outer surface due to pull out effects.[6] In summary, this research provides a new outlook for various applications such as biomedicine [7], photodetectors [8] and for light absorbing and harvesting of solar energy [9]. In addition, it serves as an eye-opener for the potential of semiconductor surface chemical studies using an UHV-integrated chemical cell connected to XPS to study etching systems. [1] R. Pillarisetty, Nature 479 (2011), p. 324-328. [2] J. Ryckaert et al., IEDM San Francisco, CA, USA, pp. 29.4.1-29.4.4 (2019) [3] K. Wostyn, F. Sebaai, J. Rip, H. Mertens, L. Witters, R. Loo, A. Y. Hikavyy, A. Milenin, N. Horiguchi, N. Collaert, A. Thean, P. Mertens, S. De Gendt and F. Holsteyns, ECS Trans., 69, 147 (2015). [4] M. Kobayashi, G. Thareja, M. Ishibashi, Y. Sun, P. Griffin, J. McVittie, P. Pianetta, K. Saraswat, Y. Nishi: J. Appl. Phys. 106, p. 104117-7 (2009). [5] G. H. A. Abrenica, M. V. Lebedev, G. Okorn, D. H. van Dorp and M. Fingerle, Appl. Phys. Lett., 113, 062104 (2018) [6] Graniel Harne A. Abrenica, Mikhail V. Lebedev, Mathias Fingerle, Sophia Arnauts, Nazaninsadat Bazzazian, Wolfram Calvet, Clement Porret, Hugo Bender, Thomas Mayer, Stefan de Gendt and Dennis H. van Dorp, J. Mater. Chem. C, 2020, 8, 10060 (2020) [7] H. Geng, J. Dai, J. Li, Z. Di and X. Liu, Sci. Rep. 6, 37474 (2016) [8] J. Michel, J. Liu and L. C. Kimerling, Nat. Photonics 4, 527534 (2010) [9] S. L. Shinde, T. D. Dao, S. Ishii, L-W. Nien, K. K. Nanda and T. Nagao, ACS Photonics 4, 1722-1729 (2017)

In this atomic-scale study on wet etching, the importance of surface chemistry, in particular the nature of the surface oxides, is demonstrated for technologically relevant group IV semiconductors, Ge and SiGe. Elemental quantification of Ge in hydrochloric acid solution containing hydrogen peroxide showed a striking impact of the Si bulk concentration on the kinetics of etching. Postoperandosurface analysis provided insight into the oxide product formed after etching: a non-homogeneous porous layer with a depletion of Ge components at the outer surface due to pull out effects. Oxide formation was verified by microscopic imaging. We provide basic reaction schemes that help to elucidate the results.

Herein, we investigate wet-chemical etching of Ge (100) in acidic H2O2 solutions for technologically advanced device processing. Nanoscale etching kinetics data were provided by inductively coupled plasma mass spectrometry (ICP-MS) measurements. Rotation rate- dependent measurement showed that the hydrodynamics of the system is important. The dependence of the etch rate on the HCl concentration was considered for the range 0.001–1 M HCl. A stark difference morphologically for >1 M HCl, which resulted in a rough surface confirmed by atomic force microscopy (AFM) images, has been observed. X-ray photoelectron spectroscopy (XPS) measurements provided insight in the surface chemistry of etching for device processing. Electrochemical measurements confirmed that the etching process follows a chemical mechanism. Based on X-ray photoelectron spectroscopy (XPS) data, we present reaction schemes that help to understand the results.

Factors determining etching and passivation of n-type InP in H2SO4 and HCl solution and the corresponding surface chemistry are considered. Passivation is favoured by higher light intensity and lower proton and Cl− ion concentration. Ex-situ surface analysis shows the passive (bi)layer to consist mainly of oxide-based In3+ and P5+ components: InPO4 and In(PO3)3. Hydrodynamics is found to play a decisive and surprizing role in determining the kinetics of the surface reactions. Oxygen-bridge formation between surface In and P atoms, as a result of deprotonation of a P-OH reaction intermediate, is considered to be important in determining competition between the two reaction paths: etching and passivation. These results are compared with markedly contrasting results for n-type GaAs under similar experimental conditions.

With increasing challenges in reducing power density while keeping and even increasing the device performance at every new technology node, innovations in both the device architecture and materials will be needed to ensure continuous improvements in power, performance, area and cost. For the last decade, replacing the Si channel by higher mobility materials like III-V and (Si)Ge has been considered as one of the most challenging innovations needed to further scale down the supply voltage and improve the overall energy efficiency of CMOS circuits. While these materials will not only contribute to enhancing the standard CMOS performance, the possibility of integrating these materials on a Si platform opens exciting new opportunities to build unique circuits, systems and applications. Especially in RF applications, co-integration of III-V/GaN and Si CMOS might be the key enabling technology to provide the speed and power efficiency required for next generation mobile communications. While the device architectures under consideration differ from nowadays ultra-scaled FinFET and nanowire/nanosheet technologies, and their scaling in general is more relaxed, there are significant challenges related to integrating these components on Si substrates. It will need innovations in patterning, deposition and cleaning, next to addressing the challenges of handling these novel materials in a standard CMOS environment. In this work, we will review the status and integration challenges of these materials for both advanced CMOS technologies and RF applications. Focus will be put on the required advancements in etch and deposition needed to enable the integration of these novel materials and devices on a Si platform.

Recently, Germanium (Ge) has gained a massive attention from different research fields like energy1-2, photonics3-4, biomedicine5, and most importantly, nanoelectronics6. Historically, Ge was the very first semiconductor utilized as a key material for transistors by John Bardeen, William B. Shockley and Walter H. Brattain but was abandoned because of its low purity, narrow band gap and chemically unstable oxide.7 From being left behind, after silicon (Si) found its way to fame, Ge is now enjoying resurgence in the world of CMOS devices.8 Due to the extreme size scaling of Si-based complementary metal-oxide semiconductor (CMOS) devices, performance enhancement can no longer be achieved due to intrinsic mobility issues, which can be compensated by the higher carrier mobility of Ge.9 In this context, Ge is a promising candidate to replace Si. Hence, central understanding in Ge surface and interface chemistry is currently indispensable for the development of novel nanodevice applications. In this work, we report the very first formation of Ge pyramids through electrochemical etching and its surface chemistry in HCl solutions under applied potential conditions. As a starting point, voltammetric (j-V) measurements were performed for a large concentration range of the acid (Figure 1a). In all cases in the plateau region (at 0.8V), a linear increase in photocurrent density with increasing light intensity was measured (Figure 1a inset). These results are attributed to a high oxide solubility and, consequently, low oxide coverage (supported by XPS results). No characteristic oxide passivation is observed during anodic etching of n-type Ge, even in the case of a very dilute 0.05 M HCl solution and current densities as high as ~6.0 mA cm-2. Morphological studies (AFM and SEM) revealed a striking and unexpected anisotropy in the surface chemistry of etching for high HCl concentrations, evidenced by the formation of random pyramids with characteristic (111) facets (Figure 1b). For Si, patterning can be used to further lower reflectance and hence improve light coupling effects. In order to scrutinize if similar effects can be observed for Ge, we fabricated a honeycomb template with circular openings of 1 mm to expose the Ge via photolithography. After photoanodic etching of the patterned Ge sample at 0.8 V in 8 M HCl solution, highly ordered pyramidal structures were obtained which lowered the reflectance further by 6% as presented in Figure 1c. This shows that light coupling effects are very likely vital. Integrated electrochemical etching chamber connected to X-ray photoelectron spectroscopy (XPS) instrument as displayed in Figure 1d, which excludes the effect of O2 and H2O vapor from the atmosphere, was utilized. Core-level Ge3d spectra suggest that the process of pyramid texturization is induced by the presence of Ge-Cl bonds on the Ge (100) surface during photoanodic dissolution (Figure 1e). A strong decrease in Ge-OH upon increasing the HCl concentration from 1 M to 8 M is accompanied by an increase in chemically bonded Cl, supported by the chemical shift of 0.6 eV. As the Cl content is similar based in Cl 2p (data not shown), it is very likely that for lower HCl concentration, with less Ge-Cl, physisorption of the halide ion is more important. While, at high HCl concentration, chemisorption governs. Based on these results, we propose surface electrochemical reaction schemes that relate the observed anisotropy in etching to surface chemistry. We believe that these findings are of fundamental interest and of technological importance for new developments in the fields of energy, photonics, biomedicine, and nanoelectronics. References [1] J. D. Ocon, J. W. Kim, G. H. A. Abrenica, J-K. Lee and J. Lee, Phys. Chem. Chem. Phys. 16, 22487-22494 (2014). [2] X. Li, Z. Yang, Y. Fu, L. Qiao, D. Li, H. Yue and D. He, ACS Nano 9, 1858-1867 (2015). [3] J. Michel, J. Liu and L. C. Kimerling, Nat. Photonics 4, 527534 (2010). [4] S. L. Shinde, T. D. Dao, S. Ishii, L-W. Nien, K. K. Nanda and T. Nagao, ACS Photonics 4, 1722-1729 (2017). [5] H. Geng, J. Dai, J. Li, Z. Di and X. Liu, Sci. Rep . 6, 37474 (2016). [6] J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan and C. M. Lieber, Nature 441, 489-493 (2006). [7] R. C. Jaeger, Introduction to Microelectronic Fabrication, second ed., Prentice Hall, New Jersey, 2002. [8] R. Pillarisetty, Nature 479, 324-328 (2011). [9] M. Kobayashi, G. Thareja, M. Ishibashi, Y. Sun, P. Griffin, J. McVittie, P. Pianetta, K. Saraswat and Y. Nishi, J. Appl. Phys. 106, 104117-7 (2009). Figure 1

Wet etching offers an advantage as a soft, damage-less method to remove sacrificial material with close to nanometer precision which has become critical for the fabrication of nanoscale structures. In order to develop such wet etching solutions, screening of etchant properties like selectivity and (an)isotropy has become vital. Since these etchants typically have low etch rates, sensitive test structures are required to evaluate their etching behavior. Therefore, scaled-down single-crystalline Si (c-Si) and SiGe (c-SiGe) wagon-wheels were fabricated. First, the sensitivity of the c-Si wagon-wheels to detect anisotropic behavior of crystalline silicon in the alkaline etchants TMAH and NH4OH was demonstrated. Distinctive wagon-wheel patterns, characteristic for each material/etchant pair, were observed by top-down scanning electron microscopy (SEM) after anisotropic wet etching. Similar trends in crystallographic plane-dependent etch rates were obtained for both Si(100) and Si(110) substrates. Secondly, the etching of both c-Si and c-Si75Ge25 wagon-wheels in a typical selective etchant, peracetic acid (PAA), was evaluated. c-Si75Ge25 etching in PAA resulted in isotropic etching. Selectivity values were calculated based on two methods: the first by measurement of the sidewall loss of the spokes of the wagon-wheel, the second, indirect method, through measurement of the spoke retraction lengths. Both methods give comparable values, but the latter method can only be used after a certain critical etching time, after which the spoke tips have evolved toward a sharp tip.

This article reports Si-passivated Ge nFinFETs with significantly improved Gm(SAT)/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high- last process. SiO2 dummy gate oxide (DGO) deposition on Ge fin is shown to form (Si-x)Ge1-xOy, which is, compared to a pure SiO2, more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced , and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum of 0.13 V, the best Gm(SAT)/SSSAT of 5.4 is achieved, which is today's record value among the sub-100-nm- n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack.

We study the anisotropy in surface oxidation for Ge(100) and (110) in HCl/H2O2 solution complemented by synchrotron X-ray photoemission spectroscopy (SXPS) measurements integrated with an in situ etching chamber. Visual anisotropic demonstration is confirmed by lithographic Ge nanowedges.

The Gate-All-Around (GAA) architecture constructed of vertically stacked horizontal Silicon Nano-Wires (Si NWs) are a promising candidate to replace FinFET for device scaling at sub 5-nm technology nodes. In this paper, Si NWs’ release, which is the sacrificial film etching of SiGe 25% (Silicon 0.75 Germanium 0.25 ) selective to Si, will be presented. It is known that the boundary layer between Si and SiGe 25% in the multistack is very sharp, since Ge diffusion depth into Si is generally limited up to 1nm. However, the thermal annealing process is known to cause intermixing of SiGe/Si at the boundary layer with an intermixing depth ranging from 1 to 2 nm [1]. In other words, there is a possibility of Ge residue remaining at the Si NWs’ surface after the selective etch of the sacrificial SiGe 25% film using a formulated chemistry [2]. The presence of impurities on the Si NWs channel surface is expected to cause an increase in leakage current causing a degradation in device performance. Therefore, the motivation in this study is to investigate the Ge residue in Si NWs after SiGe:Si selective etching and means of removal them from the Si NWs’ surface. To investigate the surface clean, blanket wafers of 50-nm SiGe 25% on Si were prepared by epitaxial growth. The SiGe 25% layer was then removed using the formulated chemical. These wafers were analyzed by dynamic SIMS and confirmed the diffusion of Ge into Si, which indicates the need of a subsequent surface clean to remaining Ge. At first, various commodity chemicals like HF, HCl and HPM (a mixture of HCl/H 2 O 2 /H 2 O) followed by DIW rinse were evaluated; however, none of these reduced the level of diffused Ge. Similarly, there was no further Ge reduction even with additional process time with the formulated chemical. Finally, APM (a mixture of NH4OH/H 2 O 2 /H 2 O) followed by DIW rinse was investigated, and the Ge concentration on the Si surface was reduced. The H 2 O 2 oxidized Ge to Ge (OH) 2 , which subsequently dissolved in H 2 O [3][4]. Furthermore, the H 2 O 2 oxidized the Si surface to SiO 2 , which was etched by NH 4 OH. As a result, it is proposed that the intermixing layer of SiGe/Si of Si surface was etched with concomitant reduction of the Ge concentration on the Si surface [5]. The intermixing layer of SiGe/Si has a much lower Ge concentration than SiGe 25%. Therefore, the chemicals that are effective for Si etching should also be effective for removing the intermixing layer of SiGe/Si [6][7]. The result of etching the intermixing layer of SiGe/Si with these chemicals will be presented. In addition, the surface roughness compared to before post process was improved, which is also beneficial for enhancing device performance. Furthermore, the impact of the thermal budget during the annealing process on the removal performance of Ge residue and the difference of intermixing depth of SiGe/Si will be shown. Finally, the most efficient post cleaning for Si NWs will be proposed. In summary, the Ge residue remaining at the Si NWs channel surface, which could not be removed by the formulated chemistry, will be efficiently removed by etching this intermixing layer. It will be shown that an optimized clean after the Si NWs’ release can be effective in removing Ge residue from this Si channel surface. [1] H. Mertens et al., ECS Transactions, 77 (5) 19-30 (2017) [2] K. Komori et al., UCPSS.1662-9787, 282,107-112(2018) [3] K. Komori et al., ECS Transactions, 80(2) 141-146 (2017) [4] N. Cerniglia et al., J. Electrochem. Soc, 109(6) 508-125(1962) [5] G. K. Celler et al., Electrochemical and Solid-State Letters, 3 (1) 47-49 (2000) [6] J. Phys. Chem. C, 118, 4, 2044-2051(2014) [7] O. Tabata et al., Sensors and Actuators A, 34(1) 51-57(1992)

Recent developments in device technology resulted in an upsurge of interest in III-V compound semiconductors. These include improved fabrication techniques for flexible electronic devices,[1,2] and epitaxial integration of various III-V channel materials on Si-based platform wafers enabling the development of highly scaled CMOS transistors [3–5] and nanophotonic devices [6]. While fabrication strategies for traditional III-V optoelectronic devices such as light-emitting diodes, lasers and solar cells are well established, the very small dimensions of these new nanodevices pose new problems. In such applications wet-chemical etching remains an essential step. The ever decreasing size of III-V devices requires ultimately atomic-layer-scale control of surfaces in terms of etching selectivity, stoichiometry and morphology.[7,8] Considerable expertise and literature is currently available on III-V semiconductor etching[9,10]. However, much of the reported work is empirical, etch rates are high, and mechanistic insight into (electro)chemical processes occurring at the semiconductor-solution interface is often lacking. In this work an overview will be given of wet-chemical approaches for nanoscale and atomic-layer-scale etching of Ga(In)As and InP. Two types of etching systems will be discussed. The first is based on the use of acidic H2O2 solution. Inductively coupled plasma mass spectrometry (ICP-MS) measurements, used to determine etching kinetics, showed that under similar conditions the etch rate of Ga(In)As in H2SO4/H2O2 solution is more than an order of magnitude higher than that of InP. Another striking observation is the influence of the acid, H2SO4 and HCl, on etching kinetics. An increase in HCl concentration leads to an increase in the etch rate of InP while the dissolution rate of Ga(In)As is markedly lowered for the active etching range. Previous work suggested that the surface oxide or hydroxide may be important.[11,12] We have used X-ray photoemission spectroscopy (XPS) and time-of-flight elastic recoil detection analysis (ToF-ERDA) to obtain information about (hydr)oxide formation on the etched surfaces. ToF-ERDA measurements also allowed us the detect surface chlorine in the case of HCl-based etchants. The results indicate that, while the initial step (the breaking of the III-V surface bond) is the same for both semiconductors, the ease with which the resulting group V hydroxide entity at the surface can be deprotonated determines whether the etch rate will be high (Ga(In)As) or low (InP). The mechanism can also help to explain the contrasting role of HCl in the dissolution of the two semiconductors. An alternative digital type of etching approach for InGaAs and InAs involves self-limiting surface oxidation in O3/H2O followed by an oxide removal step in HCl solution[12]. ICP-MS quantification of the dissolved surface oxide species indicates that a high stoichiometry of etching is obtained and that the number of equivalent oxidized atomic layers can be controlled by adjusting the dissolved O3 concentration. For >4 cycles some surface roughening is observed, most likely due to due to the high solubility of As oxides in water. An important advantage of the 2-step approach is that defect selective etching can be effectively suppressed. Examples of applications of the two etching systems will be highlighted. [1] C.-W. Cheng, K.-T. Shiu, N. Li, S.-J. Han, L. Shi, D.K. Sadana, Nat. Commun. 4 (2013) 1577. doi:10.1038/ncomms2583 [2] N.J. Smeenk, J. Engel, P. Mulder, G.J. Bauhuis, G. Bissels, J.J. Schermer, E. Vlieg, J.J. Kelly, ECS J. Solid State Sci. Technol. 2 (2013) P58–P65. [3] J.A. del Alamo, Nature. 479 (2011) 317–323. doi:10.1038/nature10677 [4] M. Paladugu, C. Merckling, R. Loo, O. Richard, H. Bender, J. Dekoster, W. Vandervorst, M. Caymax, M. Heyns, Cryst. Growth Des. 12 (2012) 4696–4702. doi:10.1021/cg300779v [5] N. Waldron, C. Merckling, L. Teugels, P. Ong, S.A.U. Ibrahim, F. Sebaai, A. Pourghaderi, K. Barla, N. Collaert, A.V.-Y. Thean, IEEE Electron Device Lett. 35 (2014) 1097–1099. doi:10.1109/LED.2014.2359579 [6] Y. Shi, Z. Wang, J. Van Campenhout, M. Pantouvaki, W. Guo, B. Kunert, and D. Van Thourhout, Optica 4, 1468-1473 (2017). doi:10.1364/OPTICA.4.001468 [7] K.J. Kanarik, T. Lill, E.A. Hudson, S. Sriraman, S. Tan, J. Marks, V. Vahedi, R.A. Gottscho, J. Vac. Sci. Technol. Vac. Surf. Films. 33 (2015) 020802. doi:10.1116/1.4913379 [8] G.S. Oehrlein, D. Metzler, C. Li, ECS J. Solid State Sci. Technol. 4 (2015) N5041–N5053. doi:10.1149/2.0061506jss [9] P.H.L. Notten, J.E.A.M. Meerakker, J.J. Kelly, Elsevier Advanced Technology, 199. [10] A.R. Clawson, Mater. Sci. Eng. R Rep. 31 (2001) 1–438 [11] D.H. van Dorp, S. Arnauts, D. Cuypers, J. Rip, F. Holsteyns, S.D. Gendt, J.J. Kelly, ECS J. Solid State Sci. Technol. 3 (2014) P179–P184. doi:10.1149/2.021405jss [12] D.H. van Dorp, S. Arnauts, F. Holsteyns, S.D. Gendt, ECS J. Solid State Sci. Technol. 4 (2015) N5061–N5066. doi:10.1149/2.0081506jss

Ge pyramid texturization has been demonstrated via photoelectrochemical etching in HCl solution.