Volatile organic compounds (VOCs) are low-molecular-weight, high-vapor-pressure gases that readily evaporate with a distinct odor profile. In the food industry, spoilage of food products is accompanied by the release of undesirable VOCs with a rancid odor profile. Monitoring these VOCs across the farm-to-fork value chain provides crucial information on product quality and enables data-driven decision-making for consumers and stakeholders, such as logistics and cold chain operators. In particular, degradation-related VOCs in edible oils are extremely challenging to detect due to the strong masking from other aroma-related VOCs and the lack of observable visual cues. In this work, we developed a highly sensitive and specific Molecularly Imprinted Polymer (PA-MIP) functionalized VOC sensor for the detection of Pentanoic Acid. Using only a 10 mL sample volume, the PA-MIP sensor achieved a rapid response time of 5 min and a detection limit of 25 ppm for Pentanoic Acid, with at least threefold higher response compared to structurally related and fragrance-related VOCs in fragrant peanut oil. The sensor was reusable for at least ten measurement cycles without significant performance degradation and reliably discriminated artificially aged peanut oil from fresh oil. Together, these metrics position the VOC sensing system as a practical tool for real-time peanut oil freshness monitoring that strengthens food safety and helps curb food wastage.

Logic and memory transistors integrated with oxide semiconductors are promising for monolithic 3D systems that enable reconfigurable functionality and enhanced on-chip communication. However, challenges in controlling carrier mobility, carrier concentration, and defect density have hindered their deployment in advanced chip technologies. Here, we report a heterojunction oxide semiconductor channel approach that mitigates the interface/channel defect density and achieves field-effect mobility to >100 cm2/V.s, competitive with thin-film silicon channels. By engineering a bilayer oxide channel, we demonstrate a low-thermal-budget, ultra-scaled, memory-logic dual-mode ferroelectric transistor that exhibits a high on-state current of 800 µA/µm at Vd = 1 V, a positive threshold voltage, and excellent reliability with only 30 mV threshold shift after 5000s of gate-bias stress. Furthermore, it exhibits robust memory endurance exceeding 107 cycles and a fast ferroelectric read-after-write delay of 180 ns. TCAD simulation (Ginestra) reveals that performance improvement is attributed to the defect self-compensation effect in bilayer channel, which stabilizes disordered metal bonds and weakly bonded oxygen states. This work establishes a pathway towards reliable, high-performance oxide-based transistors, offering a scalable solution for next-generation low-power reconfigurable chips tailored for generative artificial intelligence.

Conformal, high-density, and high-power integration for radio frequency systems is critical to future wireless communications. Alumina ceramic offers significant potential owing to its ultra-low dielectric loss tangent. However, wireless systems that exploit alumina’s thermal advantages remain unexplored. In this work, we developed a flexible alumina-based radio frequency system that integrates active components and antenna patches on a single substrate, achieving intrinsic heat spreading and high electromagnetic performance simultaneously, while maintaining its mechanical flexibility. An X-band array prototype demonstrated uniform temperature distribution with an average reduction of 11.5 °C in the power amplifier temperature at 1.1 W dissipation, and a larger mm-wave array further validated the scalability of our strategy and its robustness at higher frequencies. These results confirm flexible alumina as a promising substrate that is a suitable electromagnetic medium with heat-spreading capability. This work also demonstrates the use of material-circuit co-optimization in which electromagnetic performance and thermal behaviors are jointly engineered.

The integration of light polarization into non-volatile memory enables angle-resolved information processing, unlocking new photonic channels for communication, computation and imaging. Yet practical polarization-sensitive memory remains rare. Here, we report a 2D rhenium disulfide (ReS2)/hafnium zirconium oxide (Hf0.5Zr0.5O2, HZO) ferroelectric field-effect transistor in which field-driven charge separation realizes polarization-resolved memory. The redistribution of photo-generated carriers at the heterostructure interface establishes an interfacial electrostatic field that modulates HZO ferroelectric domains and encodes non-volatile states. We also find that interfacial compressive stress induced by lattice mismatch shortens the Re-Re bond, which enhances the Re-Re chain anisotropy by 3.7x (from 2.67 to 9.98). Integrated into arrays for photonic neural networks, the device attains >93% accuracy on a transformer model. Leveraging the cumulative switching property of HZO with sequential optical signals, the device enables in-situ multiplication and accumulation of inputs over time, achieving 4x area saving with <1% accuracy loss. Beyond amplitude and phase, the demonstrated electro-optic device enables optical polarization as an additional information read-out, which significantly increases the information density of photonic-based computing.

Two-dimensional optical modulators often suffer from low efficiency due to defect-induced losses and light-matter interaction strength. Here we show that edge defects in solution-processed WSe2 nanosheets, arising from metallic 1 T domains at the edges and semiconducting 2H interiors, can be dynamically saturated through carrier trap filling. By tuning the nanosheet lateral size and applying optical or electrical excitation, defect states are progressively saturated, reducing nonradiative recombination and reshaping the carrier distribution within the film. This process enhances the intrinsic excitonic response, as reflected by the improved photoluminescence peak modulation efficiencies of 0.025 eV·V-1 (electro-optic) and 0.1 eV·mW-1 (opto-optic). More importantly, the carrier redistribution and trap filling induce changes in the complex refractive index (Δn + iΔk) through defect-state modulation and free-carrier (Drude-like) effects. Integrated with lithium-niobate-on-insulator micro-ring resonators, solution-processed WSe2 films deliver efficient C-band (1530-1565 nm) modulation with a tuning efficiency of 1.84 × 10-5 pm-1·mW·m2. Time-resolved measurements further confirm fast dynamics, with ~48.1 ns rise, ~79.4 ns fall, and sustained 200 ns operation ( ~ 5 MHz), which surpasses prior 2D-material OO modulators, establishing engineered defect regulation as a scalable route toward high-performance photonic integration.

We demonstrate the first lithium niobate (LN) Micro-Ring Modulator (MRM) heterogeneously integrated on a silicon photonic platform via a high-precision, back-end-of-line (BEOL) compatible micro-transfer printing (MTP) method. Fully patterned, low-loss LN devices are aligned and transferred onto CMOS-compatible Si photonic chips with high yield and sub-150 nm accuracy. The resulting hybrid MRM achieves ultra-low insertion loss (<0.6 dB), and a low half-wave voltage-length product (V pi L = 1.5 V.cm), enabled by optimized waveguide and electrode design. The approach supports both in-plane and vertical stacking on Si waveguides, offering flexible integration pathways. Verified through array-level transfer on foundry-fabricated chips with finished redistribution layers (RDL) interconnects, this scalable, non-invasive method overcomes key limitations of prior LN-on-Si techniques and enables monolithic integration of high-speed photonic I/Os for next-generation optical interconnects.

Compute in-memory (CIM) architecture offers the promise to address the data movement efficiency in data-abundant computing, especially for deep neural networks. However, their array scalability is inevitably limited by IR losses with increasing error accumulation due to the increasing wire resistance as arrays grow in size. In this work, we propose a two-transistor-one-modulator (2T1M) electro-optic memory array with an optical bitline (BL) that circumvents the BL IR loss and capacitive loading issue. In each cell, dotproducts, performed by FeFET memories operated in sub-threshold region, are summed through phase modulation of an optical signal. We apply an ultra-lowloss compact lithium niobate on insulator (LNOI) photonic modulator to realize the energy-efficient electro-optic translation. The photonic waveguide BL read-out is achieved through pairs of shared Mach-Zender Interferometers (MZI) to maximize column layout efficiency. By eliminating IR loss on the BL, we can enable up to 3750 kb array size and achieve up to 45 % inference accuracy improvement on a large-scale ALBERT transformer model compared to conventional CIM arrays.

Analog resistive random access memory (RRAM) devices enable parallelized nonvolatile in-memory vector-matrix multiplications for neural networks eliminating the bottlenecks posed by von Neumann architecture. While using RRAMs improves the accelerator performance and enables their deployment at the edge, the high tuning time needed to update the RRAM conductance states adds significant burden and latency to real-time system training. In this article, we develop an in-memory discrete Fourier transform (DFT)-based convolution methodology to reduce system latency and input regeneration. By storing the static DFT/inverse DFT (IDFT) coefficients within the analog arrays, we keep digital computational operations using digital circuits to a minimum. By performing the convolution in reciprocal Fourier space, our approach minimizes connection weight updates, which significantly accelerates both neural network training and interference. Moreover, by minimizing RRAM conductance update frequency, we mitigate the endurance limitations of resistive nonvolatile memories. We show that by leveraging the symmetry and linearity of DFT/IDFTs, we can reduce the power by 1.57 × for convolution over conventional execution. The designed hardware-aware deep neural network (DNN) inference accelerator enhances the peak power efficiency by 28.02 × and area efficiency by 8.7 × over state-of-the-art accelerators. This article paves the way for ultrafast, low-power, compact hardware accelerators.

Efficient data transfer between memory and photonic components is crucial for a wide range of applications. However, this necessity brings forth energy-efficient data movement challenges associated with the memory wall, underscoring the demand for a fast and low-energy electro-optic photonic memory solution. Here, we demonstrate a class of energy-efficient electro-optic devices, namely Pockels photonic memory, that combines low-field switchable ferroelectrics with lithium niobate's Pockel's effect. Among such devices, this article will describe in detail the integrated embodiment of a ferroelectric field-effect transistor with lithium niobate on insulator micro ring resonator. We achieve switchable and non-volatile multiple optical memory states (6 states per transistor) with ultra-low energy cost (femto Joule/state), while achieving robust 10 year data retention and read-write endurance exceeding 107 cycles. Furthermore, we demonstrate the possibility of linear memory state stacking. The Pockels photonic memory enables the scaling of reconfigurable photonic systems into the femto Joule/state energy efficiencies.

Developing a sustainable, in-situ responsive sensing method for continuously monitoring water quality is crucial for water use and quality management globally. Conventional water quality monitoring sensors face challenges in achieving ultrafast response time and are non-recyclable. We present a self-assembly approach for a closed-loop recyclable, autonomous self-healing and transparent dielectric material with nanostructured amphiphobic surfaces (termed 'ReSURF'). Our approach uses tribo-negative small molecules that spontaneously secrete onto the surface of the fluorine dielectric matrix via biomimetic microphase separation within minutes. ReSURF devices achieve millisecond water quality sensing response time (~6 ms), high signal-to-noise ratio (~30.7 dB) and can withstand large mechanical deformations (>760%, maximum of 1000% strain). We show ReSURF can be readily closed-loop recycled for reuse, underscoring its versatility. We further demonstrated its use in a soft stretchable fish-like robot for real-time water contamination (including perfluorooctanoic acid, a member of per- and polyfluoroalkyl substances (PFAS) and oily pollutants) assessments.

The growing demand for intelligent, real-time systems pushes artificial intelligence beyond the confines of centralized data centers toward distributed, edge-based applications such as autonomous robotics, mobile platforms, and IoT sensors. However, the energy and space requirements of conventional artificial intelligence (AI) hardware such as graphic processing units and AI-specific application-specific integrated circuits, pose fundamental limitations for deployment at the edge. Bioinspired computing offers a compelling alternative, emulating the efficiency and adaptability of biological systems to achieve low-power, real-time intelligence. Among these approaches, spiking neural networks stand out for their sparse, event-driven computation and have demonstrated orders-of-magnitude energy efficiency gains on neuromorphic platforms such as SpiNNaker and Intel's Loihi. Yet, to realize the full potential of bioinspired intelligence in edge environments, a new class of customized hardware is imperative. Emerging innovations in material science, particularly the integration of 2D materials, can enable the design of compact, reconfigurable neuromorphic devices that mimic complex neuronal dynamics with minimal power consumption. These advances promise a new generation of scalable, multifunctional edge AI systems that are capable of perception, adaptation, and autonomous decision-making, heralding a transformative leap in energy-efficient computing for pervasive intelligent technologies.

We introduce a CMOS-compatible hybrid method combining dry etching and wet polishing, achieving ultra-low-loss lithium niobate waveguides (0.28 dB/cm) and high-Q microrings (Q = 1.4× 106), enabling scalable integration of lithium niobate photonic networks. © 2025 The Author(s)

Solution-processable 2D materials (2DMs) are gaining attention for applications in logic, memory, and sensing devices. This review surveys recent advancements in memristors, transistors, and sensors using 2DMs, focusing on their charge transport mechanisms and integration into silicon CMOS platforms. We highlight key challenges posed by the material’s nanosheet morphology and defect dynamics and discuss future potential for monolithic 3D integration with CMOS technology.

Antiferromagnets hosting real-space topological textures are promising platforms to model fundamental ultrafast phenomena and explore spintronics. However, they have only been epitaxially fabricated on specific symmetry-matched substrates, thereby preserving their intrinsic magneto-crystalline order. This curtails their integration with dissimilar supports, restricting the scope of fundamental and applied investigations. Here we circumvent this limitation by designing detachable crystalline antiferromagnetic nanomembranes of α-Fe 2 O 3 . First, we show—via transmission-based antiferromagnetic vector mapping—that flat nanomembranes host a spin-reorientation transition and rich topological phenomenology. Second, we exploit their extreme flexibility to demonstrate the reconfiguration of antiferromagnetic states across three-dimensional membrane folds resulting from flexure-induced strains. Finally, we combine these developments using a controlled manipulator to realize the strain-driven non-thermal generation of topological textures at room temperature. The integration of such free-standing antiferromagnetic layers with flat/curved nanostructures could enable spin texture designs via magnetoelastic/geometric effects in the quasi-static and dynamical regimes, opening new explorations into curvilinear antiferromagnetism and unconventional computing.

Two-dimensional (2D) materials hold significant potential for the development of neuromorphic computing architectures owing to their exceptional electrical tunability, mechanical flexibility, and compatibility with heterointegration. However, the practical implementation of 2D memristors in neuromorphic computing is often hindered by the challenges of simultaneously achieving low latency and low energy consumption. Here, we demonstrate memristors based on 2D cobalt phosphorus trisulfide (CoPS3), which achieve impressive performance metrics including high switching speed (20 ns), low switching energy (1.15 pJ), high switching ratio (>400), and low switching voltages (1.05 V for set and -0.89 V for reset). The creation of sulfur vacancies in CoPS3 through an electroforming process facilitates the formation of conductive filaments, leading to uniform fast switching with minimal energy requirements. The CoPS3 memristors also show linear conductance modulation and long-term memory retention, enabling high-accuracy modeling of artificial neural networks for handwritten digit recognition and convolutional neural networks for image processing. Furthermore, robust memristive switching is achieved in solution-processed large-scale CoPS3 films, underscoring their potential for wafer-scale, low-temperature integration. The combination of rapid switching, low energy consumption, extended memory retention, high switching ratio, linear conductance update, and scalability manifests the potential of 2D CoPS3 materials for energy-efficient neuromorphic computing circuits.

For system-technology co-design (STCO) of BEOL compatible beyond-Silicon heterogeneously integrated (Oxide & 2D material) materials, we investigated the monolithic 3D integration of vertically stacked 1T1R and 2T0C1R DRAM-RRAM hybrid memory array with IGZO FETs and $\text{MoS}_{2}$ analog RRAMs for low voltage switching. Our wafer-scale process $(< 400^{\circ}\mathrm{C})$ demonstrates good device performance. The ITO-enhanced IGZO selecting transistors $\left(\mathrm{I}_{\text{on}}=196.5 \mu \mathrm{A} / \mu \mathrm{m}, \mathrm{I}_{\text {off }}=1 \text{pA} / \mu \mathrm{m}\right. at \left.\mathrm{V}_{\mathrm{d}}=1 \mathrm{V}\right)$ integrated with solution deposited $\text{MoS}_{2}$ switching layer (3.6 nm), enable 1T1R memory cells with programming current $< 100\mu \mathrm{A}$ and voltage $< 1\mathrm{V}$, compatible with CMOS logic core voltages. Furthermore, to address RRAMs endurance limitations, we propose an ultra-compact vertically stacked 2T0C1R gain cell DRAM-RRAM hybrid using dual-gated IGZO FET. We also propose an all-IGZO buffer capable of 3D BEOL data pipelining for concurrent multi-stacked array operations. Such 3D analog compute-in-memory architecture significantly reduces ADC energy overheads, achieving 121 TOPS/W efficiency and 4.73 TOPS throughput.

Wearable devices can provide timely, user-friendly, non- or minimally invasive, and continuous monitoring of human health. Recently, multidisciplinary scientific communities have made significant progress regarding fully integrated wearable devices such as sweat wearable sensors, saliva sensors, and wound sensors. However, the translation of these wearables into markets has been slow due to several reasons associated with the poor system-level performance of integrated wearables. The wearability consideration for wearable devices compromises many properties of the wearables. Besides, the limited power capacity of wearables hinders continuous monitoring for extended duration. Furthermore, peak-power operations for intensive computations can quickly create thermal issues in the compact form factor that interfere with wearability and sensor operations. Moreover, wearable devices are constantly subjected to environmental, mechanical, chemical, and electrical interferences and variables that can invalidate the collected data. This generates the need for sophisticated data analytics to contextually identify, include, and exclude data points per multisensor fusion to enable accurate data interpretation. This review synthesizes the challenges surrounding the wearable device integration from three aspects in terms of hardware, energy, and data, focuses on a discussion about hybrid integration of wearable devices, and seeks to provide comprehensive guidance for designing fully functional and stable wearable devices.

Competitive‐learning‐based spiking neural networks are capable of rapid, highly accurate pattern recognition with minimal data through denoising mechanisms provide by adaptive interneuron inhibition. However, hardware implementations of such networks are currently area‐inefficient due to the high device count require to execute dual excitatory‐inhibitory synapses. To mitigate this, n‐ / p‐ reconfigurable tungsten diselenide memtransistors is introduced that can execute excitatory and inhibitory synapses in a highly compact bio‐inspired feature extractor hardware architecture. The reconfigurability is realized through a dual mode memory device with a flash‐memory‐like floating‐gate for n‐ / p‐ programing and a memristor‐like selenium vacancy‐based resistive switching that varies in memristive output with majority carrier modulation. Through a device‐system codesign, an effective 27% device count reduction in the peripheral circuits is achieved , which ameliorates circuit component congestion and circuit complexity. Compared to the prevalent winner‐takes‐all approach, the proposed machine learning with adaptive interneuron inhibition achieves high‐accuracy convergence with up to five times smaller training dataset. This accelerated learning can potentially enable edge‐artificial intelligence (AI) processors capable of ultra‐low‐energy training with limited data.

With high device integration density and evolving sophisticated device structures in semiconductor chips, detecting defects becomes elusive and complex. Conventionally, machine learning (ML)-guided failure analysis is performed with offline batch mode training. However, the occurrence of new types of failures or changes in the data distribution demands retraining the model. During the manufacturing process, detecting defects in a single-pass online fashion is more challenging and favoured. This paper focuses on novel quantile online learning for semiconductor failure analysis. The proposed method is applied to semiconductor device-level defects: FinFET bridge defect, GAA-FET bridge defect, GAA-FET dislocation defect, and a public database: SECOM. From the obtained results, we observed that the proposed method is able to perform better than the existing methods. Our proposed method achieved an overall accuracy of 86.66% and compared with the second-best existing method it improves 15.50% on the GAA-FET dislocation defect dataset.

Enhancing the ubiquitous sensors and connected devices with computational abilities to realize visions of the Internet of Things (IoT) requires the development of robust, compact, and low-power deep neural network accelerators. Analog in-memory matrix-matrix multiplications enabled by emerging memories can significantly reduce the accelerator energy budget while resulting in compact accelerators. In this article, we design a hardware-aware deep neural network (DNN) accelerator that combines a planar-staircase resistive random access memory (RRAM) array with a variation-tolerant in-memory compute methodology to enhance the peak power efficiency by 5.64× and area efficiency by 4.7× over state-of-the-art DNN accelerators. Pulse application at the bottom electrodes of the staircase array generates a concurrent input shift, which eliminates the input unfolding, and regeneration required for convolution execution within typical crossbar arrays. Our in-memory compute method operates in charge domain and facilitates high-accuracy floating-point computations with low RRAM states, device requirement. This work provides a path toward fast hardware accelerators that use low power and low area.