In this paper, we discuss a new development of 40nm SONOS eSTM™ (embedded Select in Trench Memory). We present an experimental study based on hot carrier injection mechanism for both programming/erase operations, performed on this new eNVM architecture. The optimization of drain and select gate biases, in order to define the programming and erasing threshold voltages, is also detailed. All the characterizations have been carried out for two different SONOS eSTM™ architectures giving an opportunity to propose different solutions. One of this using a continuous silicon nitride layer for two neighbour cells, taking advantage on the discrete charge trapping nature. As well, we performed endurance tests up to one million cycles for both architectures to evaluate the memory endurance.
This work presents a comprehensive analysis of electrothermal effects in emerging 3D vertical junctionless nanowire transistors (VNWFETs) using on-wafer measurements under a wide range of temperature and validated against numerical and compact model simulations. Experimental observations indicate an increase of the drain current with the temperature, conforming to the behavior of junctionless FETs. Multiphysics simulations reveal formation of temperature hot-spots that adversely affect thermal conductivity in smaller geometries. The VNWFET compact model was then modified to account for the underlying electro-thermal effects as well as dynamic self-heating. Model simulations and the experimental results at different measurement temperatures for different transistor geometries show good agreement. The developed SPICE-compatible compact model was then used for studying the impact of electrothermal effects on the performances of basic 3D logic circuits.
We present an analytical model to reproduce the non-monotonic temperature dependence of Time-Dependent Dielectric Breakdown (TDDB) in galvanic isolators based on polymeric dielectrics. The model is based on the concurrent action of two competing mechanisms involved in the TDDB dynamics, namely the worsening of the polymer dielectric strength due to moisture and the outdiffusion of water molecules during the electrical stress phase. By catching the most relevant features of the temperature dependence of TDDB in a simple yet effective way, the model represents a valuable tool to support the design of galvanic isolators based on polymeric dielectrics.
In this work, we investigate the intrinsic cycle-to-cycle variations in a spiking temperature-sensitive neuron, based on the resistive switching of a Vanadium dioxide (VO 2 ) two-terminal device. We study how this phenomenon impacts the spike rate jitter, and affects the spiking sensor precision. To do so, we combine a statistical analysis of the device DC characteristics, with measurements of the spiking neuron in dynamic operation from 41 to 47 °C. Using an analytical dynamic model, we reveal that the VO 2 cycle-to-cycle variations of the insulating resistance and insulator-to-metal threshold voltage dominate the stochastic processes. Our spiking sensor achieves large, linear sensitivity (1.71 kHz/°C) and high resolution (0.024 °C for a 10 ms-long observation), attributed to its small cycle-to-cycle variations.
RF Front-End Modules (FEM) for both smartphones and infrastructure are today deployed thanks to several technologies (GaAs, GaN, LDMOS, SiGe and RFSOI). RFSOI technology has already completely replaced GaAs for RF switches integration, but due to its very good cost/performances trade-off, RFSOI technology is also a good candidate to enable RF FEM System On Chip (LNA, PA and RF Switch on the same die). We present in this paper the development on 300-mm wafer of a cost-optimized 40-nm PDSOI technology targeting 5G wireless networks from sub-6 GHz up to mmW frequencies. Elementary devices and circuits measurements are reviewed to illustrate achievable performances.
HICUM/L2 model extensions for accurate scalable compact modeling of a state-of-the-art InP/InGaAs DHBT technology are presented. It is shown that the resulting HICUM/L2 model is suitable to predict the transistor behavior under large-signal conditions at high output power. The impact of self-heating on the safe-operating-area is discussed.
The open-circuit voltage is a key parameter determining the harvesting capabilities of diodes operating in photovoltaic regimes. It is highly dependent on temperature which may limit the diode operation in application scenarios with large temperature variations. This dependence has not been studied for diodes integrated into standard IC fabrication technologies. We present an analytical model to study the phenomenon. On one hand, it was validated with TCAD simulations within a wide operation range. On the other hand, the model was validated with experimental results with integrated diodes in two different 180 nm fabrication technologies. Results show the model qualifies to study how temperature variations affect the performance of solar cells.
New extended drain field effect transistors, EDNFET and EDPWNFET, with technology and layout optimization for mmW PA on 22FDX technology is carefully carried out in this work. Optimization through work-function engineering, gate resistance routing at PA array, and drain extension through multiple contact to poly pitch (CPP) results in 20% reliability enhancement while not sacrifice on-resistance (Ron). 2 Stage PA consist of optimized device as output stage shows a 2x improvement in output power (Pout) reaching 23dBm as well as 3% PAE enhancement at 28Ghz. To our knowledge, this is the best result we see on the 22FDX ® technology at 28Ghz
This work reports on NPN Si/SiGe heterojunction bipolar latch-up memory selectors integrated in 300mm wafers. The selector height has been scaled down to sub-100nm dimensions. The Ge concentration is varied from 25% to 45%. The device obtained features an ON-current (I ON ) in the negative branch above 6MA/cm 2 , and a non-linearity (NL) exceeding 10 5 hence meeting the STT-MRAM selector target specifications. Further, these selectors exhibit stable characteristics over 10 9 pulses.
We investigate the temperature-dependent RF response of different types of silicon substrates (standard, high-resistivity and trap-rich) through measurements performed on BEOL-embedded inductors from room temperature down to 7K. For the first time, we observe that the performance ranking between substrates, well known at 300K, is altered in cryogenic conditions (T<50K). Based on a parametric analysis of the Q-factor, we attribute this behavior to the heightened importance at low T of counteracting a parasitic surface conduction (PSC) forming at the interface between the substrate and the dielectric.
Analog circuits are sensitive to device variations. Random device variations are well modeled and quantified in the literature, but analog-relevant distance-dependent device variation measurements have not been reported for newer technology nodes. To reduce the impact of distance-dependent variations, layout patterns such as common-centroid are often used. However, these patterns use larger area and have higher parasitics than clustered (NonCC) patterns in FinFET technologies where unit parasitics are higher and design rules are more complex. This work measures variations on multiple dies in a 12nm FinFET technology, each with about 10,000 devices, and models the distance-dependent component. We then apply these findings to show that NonCC patterns can be used in lower-resolution DACs to meet mismatch specifications while reducing layout area.
Both from a scalability and integration perspective, CMOS-based qubits hold great potential for quantum computing applications. However, current fabrication processes must be adapted to fit qubit requirements, implying a need for controlled process monitoring to compare technological splits as well as to guarantee future process quality. The switch to isotopically-enriched 28 Si as a channel material is one such adaptation that requires deeper study. Here, we fabricate identical devices with 28 Si and natural Si and present a comparison of their variable-temperature transport characteristics using the Hall effect and split C-V. Once validated, we use the same 300mm process flow to fabricate 28 Si quantum dots which, despite the addition of a second gate level, display state-of-the-art charge noise at 400mK.
The read current margin and memory window (MW) of HfO2-based ferroelectric FET (FeFET) are comprehensively re-evaluated by considering the impacts of the ferroelectric dynamics and interface charges during the read operation. It is found that readout methods and read time can significantly influence the evaluation of MW and read current margin due to polarization switching dynamics, revealing the limitation of prevailing MW evaluation method by pulsed IV. Moreover, when fast readout, MW of FeFET with optimized interface traps and interlayer capacitance can be theoretically potential to be higher than 2 times of coercive voltage which is the theoretical maximum value for quasi-static readout. For practical FeFET, the high trapped charge density may not only reduce MW and read current margin, but also lead to negligible dependence on read time and method. Based on the comprehensive physical discussion, the new understanding and design strategies of FeFET with high-read-margin are provided.
In this work a TCAD model of a ferroelectric VNAND device is developed and validated against experimental data. After its accuracy is demonstrated it is then used to explore a number of issues related to the future potential of such devices including: the expected performance if negative trapping effects are reduced, the variability issues created by the polyphasic nature of hafnium-based ferroelectric films, the issue of the destructive nature of the read sweep, and poor effect of ERS pulses. In addition, some mitigation strategies to combat these issues are briefly discussed.
DCR drift (ΔDCR) modeling in Single-Photon Avalanche Diodes (SPADs) is proposed based on hot-carrier degradation (HCD) mechanism. The bond dissociation rate constant is modeled at various stress temperatures and voltages by the carrier energy distribution coupled with the current density considering carriers reaching the mean threshold Si-H bond dissociation energy. The carrier distribution energy was achieved by a Full-Band Monte-Carlo simulation accounting for the band structure and the scattering mechanisms. Hot electrons contributes mostly to the degradation of the top SPAD interface. The carrier density is then extracted from dark- and photo-generated currents together with multiplication current by means of experiment and modeling. ΔDCR is then computed by integrating the carrier generation rate from these stress-induced defects together with the position-dependent breakdown probability. This physic-based compact model allows to predict ΔDCR along stress time under a whole set of characterization and stress conditions.
TCAD finite element methods coupled with first-principles simulation are undertaken to predict the enhancement of the optoelectronic performance in highly-strained semiconductors. The increase of the absorption coefficient in strained silicon is first computed using first-principles theory and leads to significant improvement in the infrared spectrum. The absorption limit is moved from 1.1 µm wavelength in relaxed silicon to above 1.35 µm when 2% tensile strain is applied along the [110] crystal direction. A strained silicon photodetector with three thicknesses (1 µm, 10 µm and 50 µm) is then simulated using TCAD software to retrieve the strain-enhanced quantum efficiency. The results are compared to a theoretical model and show significant improvement. An increase from 0.03% to 1.92% (resp. 0.11% to 7.60%) is observed for 10 µm (resp. 50 µm) thickness at a photon wavelength of 1.2 µm. The combined approach of using TCAD tool to predict the performances of a novel photodetector for which the material properties have been computed using first principles brings new possibilities for the investigation of advanced devices.
An investigation about Low Voltage CMOS (LVCMOS) flicker noise (FN) variability and Random Telegraph Noise (RTN) occurrence, including the impact of geometric parameters (channel Width, Length and number of gates, NG), Source/Drain pocket implant and layout solutions, has been carried out, focusing on Smart Power Technology 1.8V Nch transistors used in analog applications.
With a novel laminated well isolation technology for complementary tunnel FET (TFET) devices, this work experimentally demonstrates the first bulk Si TFET-based circuits and hybrid TFET-CMOS circuits based on a 300mm CMOS foundry platform. By utilizing the proposed DTCO workflow, the designed novel laminated isolation well for bulk TFET can successfully suppress the parasitic leakage current between adjacent TFET devices without area penalty. Both all TFET-based logic gates and SRAM cells are experimentally demonstrated and verified, indicating the validity of proposed well isolation technology. Moreover, benefiting from the proposed monolithic integration process with CMOS, there are no parasitic leakage current paths between adjacent TFET and MOSFET, enabling the first experimental demonstration of hybrid TFET-CMOS circuits including logic gates and 5-stage ring oscillator (RO). This work promotes the realization of high-energy-efficient and large-scale circuits based on TFET-CMOS hybrid foundry platform towards power- and cost-constraint AIoT applications.
Field-effect transistors (FETs) based on two-dimensional (2D) semiconductors must have ultrathin gate dielectrics in order to achieve low voltage operation. Here we achieve conformal HfO 2 gate dielectrics on monolayer MoS 2 with the aid of an AlO x seed layer deposited by "nanofog," a low temperature process at 50 °C. We study the uniformity of the nanofog layer as a function of its deposition temperature, and we also compare FETs fabricated with nanofog AlO x seed vs. electron-beam evaporated Al seed layers, followed by HfO 2 dielectric. With the nanofog seed, we achieve subthreshold slope < 100 mV/dec at room temperature and equivalent oxide thickness (EOT) of 1.3 nm. Devices with nanofog exhibit nearly hysteresis-free behavior, unlike those with the Al seed, consistent with the subthreshold data showing fewer interface defects with nanofog seed layers. The "nanofog" process is thus established as a low-temperature, industry-compatible seed layer for high-κ dielectric deposition onto 2D semiconductors.
